1. Field of the Invention
The present invention relates to integrated circuit devices and the fabrication of such devices and, more particularly, to semiconductor devices having a gate electrode with improved electrical characteristics and a method of making same.
2. Description of the Related Art
In the field of semiconductor integrated circuit devices, design features, e.g., gate length, channel length, are being steadily decreased in order to achieve higher package densities and to improve device performance. The rapid advance of field effect transistor design has affected a large variety of activities in the field of electronics in which the transistors are operated in a binary switching mode. In particular, complex digital circuits, such as micro-processors and the like, demand fast-switching transistors. Accordingly, the distance between the drain region and the source region of a field effect transistor, commonly referred to as the channel length or gate length dimension, has been reduced to accelerate the formation of a conductive channel between a source and a drain electrode as soon as a switching gate voltage is applied and, moreover, to reduce the electrical resistance of the channel.
Thus, a transistor structure has been created where the longitudinal dimension of the transistor, commonly referred to as the width dimension, extends up to 20 xcexcm, whereas the distance of the drain and source, i.e., the gate length, may be reduced down to 0.2 xcexcm or less. As the gate length of the channel has been reduced to obtain the desired switching characteristic of the drain-source line, the length of the gate electrode is also reduced. Since the gate electrode is typically contacted at one end of its structure, the electrical charges have to be transported along the entire width of the gate electrode, i.e., up to 20 xcexcm, to uniformly build up the transverse electric field that is necessary for forming the channel between the drain and source regions. Due to the small length of the gate electrode, which usually consists of polycrystalline silicon, the electrical resistance of the gate electrode is relatively high, and it may cause high RC-delay time constants. Hence, the transverse electrical field necessary for fully opening the channel is delayed, thereby further deteriorating the switching time of the transistor line. As a consequence, the rise and fall times of the electrical signals are increased and the operating frequency, i.e., the clock frequency, has to be selected so as to take into account the aforementioned signal performance.
In view of the foregoing, the switching times of field effect transistors are no longer only limited by the drain and source characteristics, i.e., dimension and resistance, but also significantly depend on the signal propagation along the gate electrode. However, the resistance of the gate electrode affects the propagation time of a signal along the gate width direction. To minimize the electrical resistance of the drain and source regions, as well as that of the gate electrode, a silicidation process is usually performed in which a portion of the aforementioned regions are transformed into a metal silicide region in order to lower the respective electrical resistances. The depth of the metal silicide regions on the surfaces of the drain region, source region and gate electrode is limited by the requirements for the integrity of shallow drain/source junctions. That is, the metal silicide regions can only be made a certain thickness without adversely impacting the source/drain regions.
With reference to FIGS. 1A-1C, an illustrative example of forming a MOS transistor according to a typical prior art process will be described. It is to be noted that the drawings in this application are merely schematic depictions of the various stages in manufacturing the illustrative device under consideration. The skilled person will readily appreciate that the dimensions shown in the drawings are not true to scale, and that different portions or layers are not separated by sharp boundaries as portrayed in the drawings but may instead comprise continuous transitions. Furthermore, various process steps, as described below, may be performed differently depending on particular design requirements. Moreover, in this description, only the relevant steps and portions of the device necessary for the understanding of the present invention are considered.
FIG. 1A shows a schematic cross-section through an illustrative MOS transistor at a specific stage of a typical prior art manufacturing process. Within a silicon substrate 1, a plurality of shallow trench isolations 2 comprised of, for example, silicon dioxide, are formed. The trench isolations 2 define a transistor active region 3 in which a channel region, a drain region and a source region will be formed. Over the transistor active region 3, a gate electrode 4 is formed. The gate electrode 4 may be comprised of a variety of materials, such as polycrystalline silicon. A thin gate insulation layer 5 separates the gate electrode 4 and the transistor active region 3. The process steps involved in patterning the gate electrode 4 are of common knowledge to the skilled person, and usually include the deposition of anti-reflecting coating (ARC) and the employment of short exposure wavelengths, such as wave-lengths in the DUV (deep ultraviolet) range, while performing the required photolithography steps. Since these procedures are commonly known, the description thereof will be omitted. Moreover, sidewall spacers 8, usually consisting of, for example, silicon dioxide or silicon nitride, may be formed adjacent the sidewalls of the gate electrode 4 for aiding the forming of drain and source regions 9.
Next, as shown in FIG. 1B, a metal layer 6 is deposited over the transistor shown in FIG. 1A. The metal layer 6 may consist of a refractory metal, such as titanium, cobalt, etc., and it is provided in order to feed a subsequent silicidation process which is initialized by a heat treatment such as rapid thermal annealing (RTA). After the heat treatment, the portion of the metal layer 6 which has not reacted with the exposed surfaces of the transistor active region 3 and the gate electrode 4 is removed.
FIG. 1C schematically shows the cross-section of the MOS transistor shown in FIGS. 1A and 1B after a further heat treatment, such as an RTA process, has been performed. Through this further heat treatment, the silicided portions of the drain and source regions 9, as well as of the gate electrode 4, are converted into a low-resistance phase, e.g., a metal silicide. Accordingly, metal silicide portions 7 are formed on the source and drain regions 9 and a metal silicide portion 10 is formed on the upper surface of the gate electrode 4. The depth of the metal silicide portion on the gate electrode 4 is limited by the depth of the drain and source regions 9. That is, using traditional silicidation processing, the thickness of the metal silicide portion 10 cannot be made too thick; otherwise, too much of the source/drain regions 9 will be consumed during the silicidation process. Accordingly, the major part of the gate electrode 4 is maintained as polycrystalline silicon having a relatively low conductivity. As previously discussed, such an arrangement will cause a delay in charge carrier transportation along the gate width, whereby the signal performance of the device deteriorates.
In view of the above-mentioned problems, a need exists for a transistor having an increased signal performance and for a method of fabricating such a device. The present invention is directed to a method of making a semiconductor device that solves, or at least reduces, some or all of the aforementioned problems.
The present invention is directed to a method of forming a low resistance metal silicide region in a gate electrode of a transistor. In one illustrative embodiment, the method comprises forming a gate stack comprised of a gate insulation layer, a gate electrode positioned above the gate insulation layer, and a cover layer positioned above the gate electrode. The method further comprises forming source/drain regions in the substrate proximate the gate electrode, forming a first layer of refractory metal above the source/drain regions and the cover layer, and converting a portion of the first layer of refractory metal to metal silicide contacts above the source/drain regions. The method continues with the formation of a process layer above the metal silicide contacts and the cover layer, planarizing a surface of the process layer to expose the cover layer, and removing the cover layer. The method concludes with the formation of a second layer of refractory metal above the gate electrode and conversion of a portion of the second layer of refractory metal to a metal silicide region above the gate electrode.